"OC-48/2.5 Gbps Interconnect Engineering Design Rules"

See also: Surface Mount Backplane Connector... Semiconductor Package Power... Case Study of Cisco Package Redesign... Case Study of Package Power... DDR-II SDRAM Technology... Infiniband Cable Equalizer... Motorola WarpLink Reference Design... ->OC-48/2.5 Gbps Design Rules... The limits of FR-4... SI & Validation of BLVDS... Gigabit Interconnects... Design of Gigabit Copper Fibre Channel... GTL+ Backplane Termination... GHz Differential Connector ... Timing of SDRAM Design... Transmission Line Skin Effects... MCM Compute Node Thermal Failure... QuickRing Backplane System Bussed Clock Architectures for ATM... Simplifying FutureBus Backplane... Infiniband and the limits... SI Solutions for GTLP... A Baker's Dozen...

Presented at the DesignCon99 Dr. Edward P. Sayre, P.E. Dr. Jinhua Chen Mr. Michael A. Baxter Abstract This paper presents suggested design and fabrication rules for successful engineering of OC-48/2.5 Gbps copper interconnects. It address device alternatives, PWB designs, connector selection, EMI considerations and termination methodologies. Each topic is supported with a short case study showing SPICE simulations of alternate approaches and outcomes. This paper will provide the technical reader with suggested guidelines for designing very high performance interconnect systems. ->This paper is available from NESA for $15.00 to cover management costs. We accept credit card payment for purchase of the papers. The requested paper will be emailed to you shortly after your order is received.

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