"Semiconductor Package Power Integrity Fundamentals"

See also: Surface Mount Backplane Connector... ->Semiconductor Package Power... Case Study of Cisco Package Redesign... Case Study of Package Power... DDR-II SDRAM Technology... Infiniband Cable Equalizer... Motorola WarpLink Reference Design... OC-48/2.5 Gbps Design Rules... The limits of FR-4... SI & Validation of BLVDS... Gigabit Interconnects... Design of Gigabit Copper Fibre Channel... GTL+ Backplane Termination... GHz Differential Connector ... Timing of SDRAM Design... Transmission Line Skin Effects... MCM Compute Node Thermal Failure... QuickRing Backplane System Bussed Clock Architectures for ATM... Simplifying FutureBus Backplane... Infiniband and the limits... SI Solutions for GTLP... A Baker's Dozen...

Presented at DesignCon Santa Clara, CA - February 2004 Dr. Edward P. Sayre, P.E. Dr. Edward P. Sayre, III Mr. Michael Baxter Abstract This Paper Addresses the Following: Introduction and technologies to be considered when analyzing package power integrity Physical description of various packages - ceramic and organic High performance package signal and power/ground transmission line topologies Segmenting the problem into manageable technology chunks Experimental characterization fixture and measurement description Impedance and Transmission measurement results Crosstalk measurements and Simultaneous Switching predictions ->This paper is available from NESA for $15.00 to cover management costs. We accept credit card payment for purchase of the papers. The requested paper will be emailed to you shortly after your order is received.

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