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"MCM Compute Node Thermal Failure - Design or Test Problem?"

See also:
Surface Mount Backplane Connector...
Semiconductor Package Power...
Case Study of Cisco Package Redesign...
Case Study of Package Power...
DDR-II SDRAM Technology...
Infiniband Cable Equalizer...
Motorola WarpLink Reference Design...
OC-48/2.5 Gbps Design Rules...
The limits of FR-4...
SI & Validation of BLVDS...
Gigabit Interconnects...
Design of Gigabit Copper Fibre Channel...
GTL+ Backplane Termination...
GHz Differential Connector ...
Timing of SDRAM Design...
Transmission Line Skin Effects...
->MCM Compute Node Thermal Failure...
QuickRing Backplane System
Bussed Clock Architectures for ATM...
Simplifying FutureBus Backplane...
Infiniband and the limits...
SI Solutions for GTLP...
A Baker's Dozen...

 

Presented at the International Test Conference - October 1996

Dr. Edward P. Sayre, P.E.

Abstract

This paper is a unique documentation of a MCM thermal failure due to inadequate signal integrity of the test fixture used for at-speed testing. An accurate SPICE model of the test fixture and MCM was developed utilizing TDR techniques and analytical representations of the test fixture elements. The SPICE analysis showed clearly that impedance mismatches within the fixture components and MCM carrier and test socket caused a significant increase in the RMS driver current and produced a 33% increase in power dissipation in each MCM I/O driver. The additional dissipation, in conjunction with the elevated temperature test environment, caused the thermal failures observed during at-speed testing.

->This paper is available from NESA for $15.00 to cover management costs. We accept credit card payment for purchase of the papers. The requested paper will be emailed to you shortly after your order is received.

 

 

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