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"DDR-II SDRAM Technology and Design Trends"

See also:
Surface Mount Backplane Connector...
Semiconductor Package Power...
Case Study of Cisco Package Redesign...
Case Study of Package Power...
->DDR-II SDRAM Technology...
Infiniband Cable Equalizer...
Motorola WarpLink Reference Design...
OC-48/2.5 Gbps Design Rules...
The limits of FR-4...
SI & Validation of BLVDS...
Gigabit Interconnects...
Design of Gigabit Copper Fibre Channel...
GTL+ Backplane Termination...
GHz Differential Connector ...
Timing of SDRAM Design...
Transmission Line Skin Effects...
MCM Compute Node Thermal Failure...
QuickRing Backplane System
Bussed Clock Architectures for ATM...
Simplifying FutureBus Backplane...
Infiniband and the limits...
SI Solutions for GTLP...
A Baker's Dozen...

Presented at DesignCon 2003, Santa Clara, CA

Dr. Edward P. Sayre, III.
Dr. Edward P. Sayre, P.E.
Mr. Michael A. Baxter, B.S.E.E.

Abstract

This paper focuses on second generation of Double Data Rate Synchronous Dynamic Random Access Memory (DDR-II SDRAM) technology and design trends. DDR-II SDRAM provides designers technical and economic benefits as compared to SDRAM and DDR-I. For example, DDR-II memory offers at least a 4 times speed increase over SDRAM and 2 or more times speed increase over DDR. DDR-II architecture offers reduced signal latency and lower power through the use of SSTL_18 transistor technology. As memory speeds and signal efficiency continue to improve, engineers need to be skillful in the design implementation of memory technologies to ensure efficient, cost-effective products. NESA’s paper will illustrate the current trends in DDR development briefly review competing technologies, introduces SSTL_18 technology and how it is applied to DDR-II SDRAM design.

In addition to retaining the use of data strobe (DQS) timing signaling, other new features implemented in DDR-II memories are register controlled On-Die Termination (ODT), Off-Chip Driver (OCD) impedance adjustment of the output drivers while maintaining backward compatibility of control commands for DDR memories. These features are facilitated by the controller, but their use depends on the programming of the controller by the system/board designer.

An illustrated case study of DDR-II clocking, and data and data strobe signal integrity simulations, including the new On-Die Termination (ODT) technology, is presented towards the end of this paper. Through this paper the technical audience will gain a solid understanding of what DDR-II SDRAM is all about and how to evaluate and implement good signal integrity in high- performance DDR-II system memory designs.

->This paper is available from NESA for $15.00 to cover management costs. We accept credit card payment for purchase of the papers. The requested paper will be emailed to you shortly after your order is received.

 

 

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