"Motorola WarpLink Reference Design Platform"

See also: Surface Mount Backplane Connector... Semiconductor Package Power... Case Study of Cisco Package Redesign... Case Study of Package Power... DDR-II SDRAM Technology... Infiniband Cable Equalizer... ->Motorola WarpLink Reference Design... OC-48/2.5 Gbps Design Rules... The limits of FR-4... SI & Validation of BLVDS... Gigabit Interconnects... Design of Gigabit Copper Fibre Channel... GTL+ Backplane Termination... GHz Differential Connector ... Timing of SDRAM Design... Transmission Line Skin Effects... MCM Compute Node Thermal Failure... QuickRing Backplane System Bussed Clock Architectures for ATM... Simplifying FutureBus Backplane... Infiniband and the limits... SI Solutions for GTLP... A Baker's Dozen...

Presented at the Motorola Smart Networks Developer Forum, New Orleans July 2002 Dr. Edward P. Sayre, III. Dr. Edward P. Sayre, P.E. Mr. Michael A. Baxter, B.S.E.E. Mr. Quang Xuan Nguyen, Motorola Ms. Thecla Chomicz, Motorola Abstract The Motorola WarpLink Reference Design Platform demonstrates the capabilities of the WarpLink 2.5 Quad SERDES device. The device was operated at wire speed of 3.125 Gbd to provide an aggregate speed of 10Gbps per device. The device's pre-emphasis/equalization feature proved indispensable for data transfer at gigabit wire speeds over long interconnects. In particular, WarpLink 2.5 Quad has demonstrated the ability to operate at, and beyond the XAUI specification of 3.125 Gbd over 50cm long channels. The WarpLink Reference Design Platform is built with common design practices, components, and PCB material (FR-4). Unrealistic and expensive gigabit design requirements - such as blind vias, drill-back, bottom-layer-only routing, and low dielectric constant PCB materials - were not required. Using a fully matured simulation and design methodology, NESA implemented a full end-to-end gigabit simulation matrix of cases. The currently available SERDES model for WarpLink 2.5 Quad was verified to emulate actual measured results. Using this modeling strategy, areas of risk for the gigabit links were identified and properly addressed while still in the design phase. The Motorola WarpLink Reference Design Platform has shown that 3.125 Gbd SERDES technology is a reality, with readily available support. Proven Reference Design Platforms and confirmed WarpLink I/O simulation models are available from Motorola. ->This paper is available from NESA for $15.00 to cover management costs. We accept credit card payment for purchase of the papers. The requested paper will be emailed to you shortly after your order is received.

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