North East Systems Associates, Inc.

 

Publications

 

About NESA
Services
Seminars
News
Publications
Home
Site Map
Search
Useful Links
Contact Us

"Case Study Power Integrity Study for Cisco Die, Package, PWB Co-Design"

See also:
Surface Mount Backplane Connector...
Semiconductor Package Power...
->Case Study of Cisco Package Redesign...
Case Study of Package Power...
DDR-II SDRAM Technology...
Infiniband Cable Equalizer...
Motorola WarpLink Reference Design...
OC-48/2.5 Gbps Design Rules...
The limits of FR-4...
SI & Validation of BLVDS...
Gigabit Interconnects...
Design of Gigabit Copper Fibre Channel...
GTL+ Backplane Termination...
GHz Differential Connector ...
Timing of SDRAM Design...
Transmission Line Skin Effects...
MCM Compute Node Thermal Failure...
QuickRing Backplane System
Bussed Clock Architectures for ATM...
Simplifying FutureBus Backplane...
Infiniband and the limits...
SI Solutions for GTLP...
A Baker's Dozen...

 

Presented at DesignCon Santa Clara, CA - February 2004

Dr. Zhiping Yang, Cisco

Abstract

This Case Study Addresses the Following:

  • Power Integrity Industry Trends
  • Source of Power Supply Noise
  • Study and Implementation on Chip
  • Study and Implementation on Package
  • Study and Implementation on Board
  • Chip, Package, Board Co-design Analysis
  • Lab Validation
  • Conclusions

->This paper is available from NESA for $15.00 to cover management costs. We accept credit card payment for purchase of the papers. The requested paper will be emailed to you shortly after your order is received. >

 

 

[About NESA] [Services] [Seminars] [News] [Publications]
[Home] [Site Map] [Search] [Useful Links] [Contact Us]

Copyright (C) 1998 - 2013 North East Systems Associates Inc.
For warranty, copyright & license information see the Legal Notices