"Signal Integrity & Validation of National's Bus LVDS (BLVDS) Technology in Heavily Loaded Backplanes"

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Prepared for National Semiconductor National's Bus LVDS (BLVDS) Technology in Heavily Loaded Backplanes Dr. Edward P. Sayre Mr. Michael Baxter Dr. Jinhua Chen Mr. John Goldie National Semiconductor - LVDS Abstract The advantages of multi-point backplane buses have been recognized for many years as offering a low cost bi-directional crossbar. But, the performance data rate has suffered because of the high current single-ended drivers in technologies such as CMOS, TTL, GTL, BTL, etc. Validated SPICE simulations show that with the use of National's DS92LV010 BLVDS transceiver devices and the optimized backplane design presented in this paper, that 20-slot multi-point backplane bus environments can operate at transmission data rates as high as 200 Mbps with adequate noise margins. The attainment of this level of performance will permit an immediate increase in throughput and a reduction in the complexity of high-bandwidth system interconnects. The National Bus LVDS (BLVDS) proto-type backplane was measured and characterized with Time Domain Reflectometry (TDR) and Time Domain Transmission (TDT) techniques. Based on the results of these measurements, an accurate SPICE model for a 20-slot, multi-point BLVDS backplane has been built and simulated. NESA-developed passive TDR SPICE simulations were used to determine the optimum backplane and termination configuration. This paper presents the optimum design parameters for high performance backplane operation at bit rates in excess of 100 MHz /200 Mbps using this revolutionary differential technology. By controlling plug-in card stub lengths, raw etch impedance, and termination values, reflections are minimized while noise margin is maximized for 20-slot bus configurations. National has achieved a fundamental breakthrough with the BLVDS family by offering CMOS differential driver/receiver solutions with low current drive requirements and high data rate performance for multi-point backplane design applications. In addition to device performance, BLVDS greatly simplifies system complexity by reducing the complex termination design required by single-ended drivers to just two passive resistors. Therefore, it does not require special termination voltages and is powered from a common rail (3.3V or 5V). In addition to adequate differential noise margins, the common mode range is greatly increased for improved noise rejection / tolerance. Noise generation is reduced through the use of current mode drivers, a small signal swing, differential data transmission, and advanced circuit design techniques. With low power dissipation, and a core CMOS process, integration of digital functions is now possible for optimized interface devices. With the level of device performance achieved, and with the system advantages in power, flexible configurations, noise tolerance and even live insertion, high performance backplane design for bandwidth hungry applications is revolutionized. ->This paper is available from NESA for $15.00 to cover management costs. We accept credit card payment for purchase of the papers. The requested paper will be emailed to you shortly after your order is received.

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